A current trend in the electronics industry is to develop applications which employ multiple cores within an application specific integrated circuit (ASIC) design. Often such applications perform a large number of concurrent activities, with each activity being performed over a different "channel" of the ASIC design. To achieve the desired level of performance, channels often must operate asynchronously as well as concurrently.
One common element typically employed between channels is a memory device (e.g., a random access memory (RAM)). However, conventional RAMs are single port (or at most dual port) devices with a first-come-first serve protocol arbitrated by a memory controller. These type of limited port devices cannot support concurrent activities over multiple channels, particularly when asynchronous operations are involved. Accordingly, a need exists for a multi-ported memory with an asynchronous and synchronous protocol.